1. Technical Field
The present disclosure relates to the field of phase locked loop, and in particular to a self-biased phase locked loop.
2. Description of the Related Art
A Phase Locked loop (PLL) is widely used in a System on Chip (SOC) to construct a frequency synthesizer, a clock generator, and the like.
A high performance PLL should ideally possess the following characteristics: low susceptibility to process, voltage, and temperature (PVT) variations; a wide frequency bandwidth; a low phase jitter and a small frequency change after being locked; a monolithic integrated filter; lower power consumption circuits, and the like.
However, it may be difficult to design a PLL having all of the above characteristics. The scaling and continuous reduction in device size introduces new challenges in designing high-speed, wide frequency bandwidth PLL chips. For example, the impact of PVT variations on PLL design typically increases with the scaling in device size.
Thus, when designing a conventional PLL, the impact of PVT variations has to be taken into consideration. Specifically, designing circuits in the conventional PLL requires an analysis of the impact of PVT variations on the stability of the PLL, and mitigating the impact of PVT variations so that the PLL is stable and meets performance requirements.
Different self-biased PLL designs have been proposed to address the problem of PVT variations. For example, the technical document titled “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VoL. 38, No. 11, November 2003 discloses a self-biased PLL circuit comprising a low-pass filter having an active resistor. U.S. Pat. Nos. 7,719,328 and 7,986,191 disclose self-biased PLLs having simplified circuit structures that can be easily implemented.
However, the PLL configurations in the prior art have some disadvantages. A PLL typically has a fixed loop bandwidth once the PLL design has been locked in. As a result, the PLL circuit may not be capable of adjusting the loop bandwidth. For example, the PLL may have a fixed loop bandwidth after the parameters (e.g. resistance and capacitance values) in the PLL circuit have been selected.
In some cases, one way to adjust the loop bandwidth in the PLL is to adjust the charge pump current. Adjusting the charge pump current may provide a wider loop bandwidth in the PLL. However, it may be difficult to achieve a programmable charge pump current (in fractions of the current, such as ½ or ¼ of the charge pump current). As a result, the programmable charge pump current has limited flexibility for adjusting the loop bandwidth. Furthermore, the programmable charge pump current may become unstable when used to adjust the loop bandwidth in a PLL (in which the circuit parameters have already been selected).